A component-level transcription of Richard F. Drushel's hand-traced
prototype schematic (serpar_working_bitmap2.tif, 15 July 2005), prepared as the basis for a
KiCad re-capture and a buildable reproduction of PCB X00257 REV 0.
| Ref | Part | Type / value | Function | |
|---|
U1 | MC6801 | 8-bit MCU, 40-pin | Main processor. Internal 2 KB mask/EPROM at $F800-$FFFF (the prototype runs the external 24-pin EPROM in expanded mode), 128 B internal RAM, three timers, and the on-chip SCI used as the AdamNet transceiver. Ports P3=AD0-AD7 (multiplexed), P4=A8-A15. | CONFIRMED |
U2 | SCN2661A | USART (EPCI), 28-pin | Signetics enhanced programmable communications interface — the RS-232 serial engine. Memory-mapped at $0100-$0103 (DATA/STATUS/MODE/COMMAND); A2/A3 undecoded so it mirrors. Baud clock from Y2. | CONFIRMED |
U3 | 74LS373 | Octal transparent latch, 20-pin | Address latch for the 6801 expanded multiplexed bus: captures A0-A7 from the AD0-AD7 lines on AS (address strobe). Pin 20=Vcc, pin 10=GND, LE from 6801 AS. Identity inferred from 8-in/8-out pinout and the presence of external memory-mapped devices that require an address latch; exact role to be confirmed on the board. | INFERRED |
U4 | 2114 | 1024x4 SRAM, 18-pin | External static RAM, low nibble. Paired with U5 for 1 KB x 8. R/W and chip-select from the decode logic. | CONFIRMED |
U5 | 2114 | 1024x4 SRAM, 18-pin | External static RAM, high nibble (paired with U4). | CONFIRMED |
U6 | MC1488 | Quad RS-232 line driver, 14-pin | TTL-to-RS-232 driver for TxD/RTS/DTR. Runs on the +/-12 V rails from U14. Inferred from the TTL->RS-232 driver block feeding the DB-25. | INFERRED |
U7 | MC1489 | Quad RS-232 line receiver, 14-pin | RS-232-to-TTL receiver for RxD/CTS/DCD. Inferred from the RS-232->TTL receiver block on the DB-25 inputs. | INFERRED |
U8 | LM339 | Quad comparator, 14-pin | AdamNet analog front end: squares up the differential AdamNet line into the 6801 SCI receive pin and generates the 1 V VREF. Labelled near the J3 AdamNet input. | INFERRED |
U9 | 74LS05 | Hex inverter (open-collector), 14-pin | Open-collector inverters wired-AND to form the memory/IO address decode (RAM select, UART select). A2/A3 are intentionally not decoded. | CONFIRMED |
U10 | 74LS04 | Hex inverter, 14-pin | Buffers R/W and the system RST line (RST inverter feeds the printer-reset and internal reset). | CONFIRMED |
U11 | 74LS08 | Quad 2-input AND, 14-pin | Combines decode terms for chip selects. | CONFIRMED |
U12 | 74LS09 | Quad 2-input AND (open-collector), 14-pin | Additional decode/strobe gating. Inferred from the 'LS09' gate labels in the decode array. | INFERRED |
U13 | 74LS01 | Quad 2-input NAND (open-collector), 14-pin | Decode/strobe gating, open-collector for the wired-AND select rails. Inferred from the 'LS01' gate label. | INFERRED |
U14 | DC-DC | +5 V -> +/-12 V converter module | Generates the +/-12 V RS-232 rails from the single +5 V supply. Marked 'DC-DC CONV' with +12 VDC and -12 VDC outputs. | CONFIRMED |
Q1 | 2N3904 | NPN transistor | Printer-reset open-collector driver to the Centronics RESET line (J1-31), and/or AdamNet transmit assist. 2.2K collector pull-up, 10K base. | CONFIRMED |
Q2 | 2N3906 | PNP transistor | AdamNet analog transmit driver stage (with U8). | CONFIRMED |
Q3 | 2N3904 | NPN transistor | Baud-rate oscillator buffer around Y2 (4.9152 MHz). Transistor type inferred. | INFERRED |
Y1 | XTAL | 6801 clock crystal | Main 6801 oscillator crystal. Value not legible on the scan — likely the ColecoVision-family 3.579545 MHz or a 4 MHz part. | OPEN |
Y2 | XTAL | 4.9152 MHz crystal | USART baud-rate clock (4.9152 MHz divides cleanly to standard bauds incl. the 38.4 k max annotated on the schematic). | CONFIRMED |
J1 | CONN_36 | 36-pin Centronics ribbon | Parallel printer port: D0-D7, Data Strobe, Paper Out, Select, Busy, and Printer Reset (J1-31). | CONFIRMED |
J2 | DB25 | 25-pin D, RS-232 | Serial port: TxD(2), RxD(3), RTS(4), CTS(5), DSR(6), SG(7), DCD/Carrier(8), DTR(20), and the 'Trapp'd Data'/'Request To Send' lines annotated by Drushel. | CONFIRMED |
J3 | CONN_9 | 9-pin D, AdamNet + power | AdamNet bus and power: pin 3=+5 V (through a 10 uH filter inductor), pin 7=AdamNet data, pin 6=AdamNet, pin 8=DC GND, pin 9=PWR GND. J3-7/J3-9 carry the net transmit/receive pair. | CONFIRMED |
SW1 | SW_3POS | 3-position mode switch | Selects Serial / Parallel / SmartWriter-passthrough output routing. | CONFIRMED |
L1 | 10uH | Filter inductor | Series inductor on the +5 V input rail at J3-3. | CONFIRMED |
D1 | LED | Power indicator LED | ON-indicator on the +5 V rail at the connector. | CONFIRMED |
Each row is a net (or bus) with the pins it connects. Bus members are abbreviated
(AD0..AD7 rather than eight rows). This is the connectivity a CAD re-capture
must reproduce.
| Net | Connects | Note | |
|---|
AD0..AD7 | U1 (P30-P37 (mux AD0-7)); U3 (D0-D7 in); U2 (D0-D7); U4 (I/O0-3); U5 (I/O0-3) | 6801 multiplexed address/data bus. Latched to A0-A7 by U3 on AS; data phase shared with the 2661 and the 2114 nibbles. | INFERRED |
A0..A7 | U3 (Q0-Q7 out); U2 (A0-A1 (RS)); U4 (A0-A9); U5 (A0-A9); U9 (decode inputs) | Latched low address. A0-A1 select the 2661 registers; A0-A9 address the 2114s; high bits feed the decode. | INFERRED |
A8..A15 | U1 (P40-P47); U9 (decode inputs) | High address from 6801 port 4, into the address decode. | INFERRED |
AS | U1 (AS); U3 (LE) | Address strobe latches U3. | INFERRED |
E | U1 (E (enable clock)); U2 (clock-qualified CE path); U9 (decode timing) | 6801 E clock, qualifies bus cycles. | INFERRED |
R/W | U1 (R/W); U10 (inverter); U2 (R/W); U4 (R/W); U5 (R/W) | Read/write, buffered by U10 to the RAM and USART. | CONFIRMED |
RST | U1 (RESET); U10 (RST inverter); Q1 (printer-reset path) | System reset; the inverted RST also drives the Centronics printer-reset. | CONFIRMED |
UART_CS | U9 (wired-AND output); U2 (CE) | USART chip-select decoded to $0100-$0103 (A2/A3 undecoded -> mirrors). | CONFIRMED |
RAM_CS | U9 (wired-AND output); U4 (CS); U5 (CS) | 2114 chip-select. | INFERRED |
TXD_TTL | U2 (TxD); U6 (driver in) | USART transmit, TTL, into the RS-232 driver. | CONFIRMED |
RXD_TTL | U2 (RxD); U7 (receiver out) | USART receive, TTL, from the RS-232 receiver. | CONFIRMED |
TXD_232 | U6 (driver out); J2 (pin 2 TxD) | RS-232 transmit to the DB-25. | CONFIRMED |
RXD_232 | U7 (receiver in); J2 (pin 3 RxD) | RS-232 receive from the DB-25. | CONFIRMED |
RTS_232 | U6 (driver out); J2 (pin 4 RTS) | Request To Send. | CONFIRMED |
CTS_232 | U7 (receiver in); J2 (pin 5 CTS) | Clear To Send. | CONFIRMED |
BAUDCLK | Y2 (4.9152 MHz); Q3 (osc buffer); U2 (BRCLK) | Baud-rate clock to the USART. | CONFIRMED |
PD0..PD7 | U1 (port (GPIO) or U3 path); J1 (D0-D7) | Centronics data lines. Whether driven from a 6801 GPIO port or a memory-mapped latch is not fully resolved on the scan. | OPEN |
DSTROBE | J1 (Data Strobe); U1 (handshake) | Centronics data strobe. | CONFIRMED |
PAPEROUT | J1 (Paper Out); U8 (input buffer chain) | Paper-out status, filtered/buffered (RC + inverter) into the 6801. | CONFIRMED |
SELECT | J1 (Select); U8 (input buffer chain) | Printer select status. | CONFIRMED |
BUSY | J1 (Busy); U8 (input buffer chain) | Printer busy status. | CONFIRMED |
PRST | Q1 (collector); J1 (pin 31 reset) | Printer reset, open-collector NPN with 2.2K pull-up. | CONFIRMED |
NET_RX | J3 (pin 7); U8 (comparator in); U1 (SCI RxD) | AdamNet receive: differential line squared by U8 into the 6801 SCI. | CONFIRMED |
NET_TX | U1 (SCI TxD); Q2 (driver); J3 (pin 7) | AdamNet transmit: 6801 SCI out through the analog driver onto the bus. | CONFIRMED |
+5V | J3 (pin 3 via L1); U1 (Vcc); U2 (Vcc); U4 (Vcc); U5 (Vcc); U14 (Vin); D1 (anode) | Main logic supply. | CONFIRMED |
+12V | U14 (+12 out); U6 (Vcc+) | RS-232 positive rail. | CONFIRMED |
-12V | U14 (-12 out); U6 (Vcc-); U7 (Vcc-) | RS-232 negative rail. | CONFIRMED |
| Question | How to resolve |
|---|
| Address latch vs. parallel-data latch (U3) | The 20-pin octal latch on the bus is captured here as the 6801 expanded-mode address latch (74LS373), because external memory-mapped devices require one. It is possible it doubles as, or is, a parallel-data latch. Resolve by tracing AS/LE and the Centronics data source on the physical board. |
| Exact decode part numbers (U12/U13) | The decode array clearly uses 74LS05 and 74LS04; the 'LS09' and 'LS01' gate labels are read with lower confidence. Confirm against the board's silkscreen/part marks. |
| Y1 crystal value | The 6801 main-oscillator crystal value is not legible on the 2005 scan. Read it off the prototype, or compute it from the firmware's AdamNet/timer constants. |
| Parallel data source (PD0..PD7) | Whether the Centronics data byte is driven from a 6801 GPIO port or a memory-mapped latch is unresolved. A short continuity trace on the board settles it. |
| Component Designation List | Drushel's title block carries a component value table, but it is below the legible resolution of this scan. A higher-DPI rescan of just that corner would recover the exact R/C values. |
| Line-driver/receiver exact parts (U6/U7) | Captured as the industry-standard MC1488/MC1489 pair on functional grounds; confirm the actual markings on the board. |
Prepared for the ColecoVision & ADAM Archive & Museum.
